Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
In multi-core architectures, multiple processor cores may be included in a single integrated circuit die or on multiple integrated circuit dies that are arranged in a single package. One or more of the processor cores may be configured in communication with one another. Each of the processor cores may be associated with one or more routers. Each of the routers may include one or more input and/or output buffers configured to store data and configured to facilitate movement of data among processor cores in the multi-core processor.